The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for assigning memory to on-chip coherence domains.
In computing, cache coherence, also referred to as cache coherency, refers to the consistency of data stored in local caches of a shared resource. When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of processing units in a multiprocessing system. Cache coherence is intended to manage such conflicts and maintain consistency between cache and memory.
A data processing system may include many processing units with many caches. Cache coherence becomes cumbersome as the number of caches grows. Coherence domains partition the caches and memory into domains. Each domain comprises one or more caches and a range of memory. Coherence domains may have varying levels of granularity depending upon the environment.
A coherence domain may contain multiple chips. In some data processing systems, a coherence domain may contain thousands of chips. Many data processing systems today have small coherence domains. Maintaining coherence incurs high overhead. Not every application needs cache coherence.